1. Field of the Invention
The present invention relates to a semiconductor memory requiring a refresh operation for retaining data written to its memory cells.
2. Description of the Related Art
A memory capacity required for a hand-held terminal such as a cellular phone is increasing year by year. Under such circumstances, a dynamic RAM (hereinafter, referred to as a DRAM) has come into use as a work memory of the hand-held terminal in place of a conventional static RAM (hereinafter, referred to as a SRAM). Since the DRAM has a smaller number of elements constituting a memory cell than the SRAM, its chip size can be made smaller and its chip cost can be made lower than those of the SRAM.
Meanwhile, power consumption of a semiconductor memory mounted on a cellular phone has to be low in order to allow long battery duration. Unlike the SRAM, the DRAM needs periodical refresh operations in order to retain data written to its memory cells. Therefore, the hand-held terminal using the DRAM as its work memory consumes power only for retaining data even when it is not in use, so that a battery is consumed.
In order to reduce power consumption of a DRAM in a standby state (in a low power consumption mode), a partial refresh technology and a twin cell technology have been developed. The partial refresh technology is disclosed in Japanese Unexamined Patent Application Publication No. 2000-298982. The twin cell technology is disclosed in Japanese Unexamined Patent Application Publication No. 2001-143463.
The partial refresh technology limits memory cells that are to retain data in a standby state, thereby decreasing the number of memory cells to be refreshed. The decrease in the number of the memory cells to be refreshed decreases the number of times of refresh operations, so that standby power consumption can be reduced.
In the twin cell technology, two memory cells (memory cell pair) respectively connected to complementary bit lines store complementary data, so that an amount of electric charges retained by the memory cell pair is doubled. Since the two memory cells retain “H” data and “L” data, respectively, a refresh cycle is determined by the longer one of the data retention times of the “H” data and the “L” data. This means that the worst data retention time is not a characteristic of one memory cell but is the sum of the characteristics of the two memory cells. On the other hand, the refresh cycle in a single memory cell is determined by the shorter one of the data retention times of the “H” data and the “L” data. Thus, the twin cell technology uses two memory cells for retaining data, so that even if one of the memory cells has a minute leak path, the other memory cell can compensate for this.